This invention relates, in general, to digital decoders for decoding digital signals and more particularly, to a CMOS decoder capable of providing one or more of n decoded outputs.
Decoders for decoding digital signals are widely used in digital systems. A digital signal can contain a group of digital bits. A message can be encoded by the group of digital bits by using a combination of the presence or absence of the digital bits. Both states, true and complement, of the digital bit is used to convey meaningful information. Decoders allow the translation of one logic word structure into another logic word structure while conserving the same information content. A decoder is often used to extract information from a complex signal. The decoder converts coded information into a more usable form.
Two digital bits can be decoded to obtain four different and distinct outputs. Three digital bits can be decoded to provide eight different outputs while four coded digital bits can provide sixteen different decoded outputs, etc., etc.
In the past, digital decoders have been rather complex and employ a great number of transistors. It is highly desirable that a decoder be small in size, yet provide fast operation, and consume a minimum amount of power.
Accordingly, it is an object of the present invention to provide a decoder of low power consumption in a minimum amount of transistors.
Another object of the present invention is to provide a versatile decoder readily adaptable for providing x of n decoded outputs where x can be any number between 1 and n, and n is the number of outputs of the decoder.